This invention relates to the field of semiconductor charge transfer devices, their fabrication and operation. The invention particularly concerns a charge coupled device (CCD) wherein the combination of a single phase clock signal, a fixed potential control gate and substrate barrier regions achieve transfer control of signal charge.
CCD arrays are relatively difficult to manufacture in comparison with many integrated circuit devices. The narrow gate spacings and overlapping gate structures required in some CCD arrays of the two, three and four phase types are known, for example, to incur inter-level and intra-level shorting difficulties. Virtual phase CCDs however employ an implanted virtual gate between adjacent metal oxide semiconductor gate electrodes and thereby operate at a fixed voltage level determined by the buried channel implant in the gate region. Such CCDs largely eliminate the gate shorting phenomenon encountered with two, three, and four phase CCD arrays. In virtual phase CCDs, however, the implant regions which form the charge conducting buried channel are somewhat difficult to control in a manufacturing environment. The implanting energy levels, heat treating and other manufacturing steps required to achieve a predetermined doping level in an implanted semiconductor region are found to be precisely determined only with carefully developed and controlled processing steps. Such processing adds undesirably to the manufacturing complexity, yield difficulty, and overall cost of this type of CCD device.
The pseudo uniphase CCD as in the present invention, does not eliminate the need for overlapping gate and implanted substrate topologies, but does significantly reduce the number of these limiting arrangements needed in a particular CCD array. The herein disclosed pseudo uniphase CCD structure also seizes upon the advantages in fabrication simplicity and device performance characteristics which flow from the use of self-aligning elements in the CCD structure. Self-aligning elements in the CCD structure both eliminate the need for close tolerance masking during the device manufacturing sequence and assure electrical locations and electrical performance which meets the expected characteristics of the CCD array.